The disclosed technique relates to methods and systems for power amplifying of signals in general, and to methods and systems for power amplifying of audio signals, in particular.
Methods and systems for amplifying electrical signals are known in the art. In general, electrical power amplifiers receive a data signal (digital or analog) and produce a respective power amplified analog signal. The type of input signal and the limitations, which are imposed on the output signal, define the structure of the power amplifier and the method, which is used for operating it. Power amplifiers are divided into several classes, according to their structure, such as class A, class AB, class D, and the like.
Conventional power-pushing elements, such as transistors (e.g., BJT, MOSFET, and the like) are made of semiconductor materials. Such power-pushing elements are characterized by a minimal operative voltage (i.e., N-type) or a maximal operative voltage (i.e., P-type). It is noted that in a given configuration, such a power-pushing element is operative to either push current or pull current (i.e., the power-pushing element can deliver current only in one direction).
The type of each of these power-pushing elements inherently limits the voltage levels, which can be amplified thereby. For example, a BJT NPN power-pushing element is characterized by a minimal operative voltage of about 0.7 volts, while defining the input signal as the voltage between the base terminal and the emitter terminal. Accordingly, a BJT NPN power-pushing element can amplify input signals, which are higher than this minimal operative voltage level. It is noted that such a power-pushing element is further limited by a maximal input voltage level, above which it saturates. Most power-pushing elements are also characterized by non-linear transfer functions.
Reference is now made to FIG. 1A, which is a schematic illustration of a class A power amplifier, generally referenced 10, which is known in the art. Class A power amplifier utilizes a single power-pushing element, which pushes current in one direction only, thereby producing only unipolar output signals. For that purpose, class A architecture converts the input signal to a unipolar signal, by shifting it completely either above or below zero level. Class A architecture includes a control unit which overcomes the minimal operative voltage problem and the inherent non-linearity of the power-pushing element.
Amplifier 10 includes a summing unit 2, a controller 4 and a power-pusher 6. Summing unit 2 is connected to a constant bias source VBIAS, referenced 8 and to controller 4. Controller 4 is further connected to power-pusher 6. Summing unit 2 receives an input signal X(t), adds VBIAS 8, and provides the result (i.e., X(t)+VBIAS) to controller 4. Controller 4 produces a respective control signal and provides it to power-pusher 6. Power-pusher 6 produces a power amplified signal Y(t) and provides it back to controller 4, as feedback. Controller 4 compares the output Y(t) with the elevated input (i.e., X(t)+VBIAS) and updates the control signal, so as to correct any errors found between the compared signals.
In general, a class A power amplifier has an output signal with a defined polarity, either positive or negative, according to the type and connectivity of the power-pushing element, which is used therefore. A class A power amplifier is characterized by high quality power amplification in terms of error between the elevated input signal and the output signal.
It is noted that the output of a class A power amplifier is biased. Hence, such a power amplifier can be implemented in systems, which are not sensitive to DC signals, such as audio systems.
The theoretical efficiency of a class A power amplifier, for a full-scale sine shaped signal is 25%. The theoretical efficiency for a full-scale typical speech or audio signal is about 8%. In class A power amplifiers, power is wasted in the form of heat. The power is mainly wasted across the power-pusher, due to the difference between the supplied power source voltage and the output voltage applied to the load.
Class AB power amplifier architecture is a bipolar power amplifier. Class AB architecture includes two power-pushing elements, one for amplifying the positive portion of the input signal and the other for amplifying the negative portion of the input signal.
Reference is now made to FIG. 1B, which is a schematic illustration of a class AB power amplifier, generally referenced 20, which is known in the art. Amplifier 20 includes a controller 22, a bias power system 24 and two power-pushers 26 and 28. Bias power system 24 is connected to controller 22, to the input terminal of positive power-pusher 26 and to the input terminal of negative power-pusher 28. The output terminals of power-pushers 26 and 28 are connected there between and further to controller 22.
In the example set forth in FIG. 1B, positive power-pusher 26 incorporates a positive power-pushing element (e.g., N-MOSFET, NPN, and the like) and negative power-pusher 28 incorporates a negative power-pushing element (e.g., P-MOSFET, PNP, and the like).
Each of the semiconductor elements used for power-pushers 26 and 28, exhibits a minimal operative voltage V1 greater than 0 and a maximal operative voltage V2 less than 0, respectively. Together, V1 and V2 define a conductance dead zone from V2 to V1. Class AB power amplifier does not allow both power-pushers to operate in the conductance dead zone. In such a situation, both power-pushers do not conduct and hence, the output signal is not defined. Accordingly, bias power system 24 always sets at least one of the power-pushers to conduct current, thereby producing a defined output signal.
Controller 22 receives an input signal X(t), produces a respective control signal and provides it to bias power system 24. Bias power system 24 modifies the control signal according to the dead zone defined by power-pushers 26 and 28 and provides a positively biased version of the control signal to positive power-pusher 26 and a negatively biased version of the control signal to negative power-pusher 28. Positive power-pusher 26 produces an output signal Y1(t), according to the positively biased control signal provided thereto. Negative power-pusher 28 produces an output signal Y2(t), according to the negatively biased control signal provided thereto. The output terminals of power-pushers 26 and 28 are short circuited together to form a common output terminal, producing an output signal Y(t). The output currents of both power-pushers 26 and 28 are summed, thus defining the output signal to be Y(t)=Y1(t)+Y2(t). Y(t) is fed back to controller 22. Controller 22 compares the output Y(t) with the input signal X(t) and updates the control signal, so as to correct any errors found between the compared signals.
A class AB architecture, compared with the class A architecture, exhibits lower quality and higher efficiency. The theoretical efficiency of a class AB power amplifier, for a full-scale sine shaped signal is 78.5%. The theoretical efficiency for a full-scale typical speech or audio signal is about 30%. In class AB power amplifiers, power is wasted in the form of heat. The power is mainly wasted across the power-pushers, due to the difference between the supplied power sources voltages and the output voltage applied to the load.
Power amplifying architecture is often influenced by the implementation thereof. For example, class D architecture is directed at situations where either the load is adapted to operate in a limited frequency bandwidth or the receiver of the produced output signal is sensitive to a limited frequency bandwidth. The frequency bandwidth of interest is defined as the cross-section between the load limited frequency bandwidth and the receiver limited frequency bandwidth. Hence, the output signal, provided to the load, can include frequencies beyond the frequency bandwidth of interest, which are discarded or ignored, according to the nature of the load and the receiver. For example, in an audio system, the speaker defines the load and the human ear defines the receiver. According to another example, in a mechanical motorized system, an electrical motor defines the load and the mechanical assembly attached thereto defines the receiver.
Reference is now made to FIG. 1C, which is a schematic illustration of a class D power amplifier, generally referenced 30, which is known in the art. Amplifier 30 includes a shaper 32 and an N-level power quantizer 34 connected thereto. N-level power quantizer 34 is operative to select from a finite set of N predetermined output voltage levels.
Shaper 32 receives an input signal X(t), produces a respective desired output signal and provides it to N-level power quantizer 34. In turn, N-level power quantizer 34 selects from the finite set of voltage levels, a voltage level, which is closest to the desired output signal and provides it as an output signal. The output signal is fed back to shaper 32, which in turn updates the desired output signal.
The input signal is usually an analog signal or a high-resolution digital signal (i.e., a digital signal comprises a large number of digitally represented analog levels). The output signal, being comprised of N (small finite number) voltage levels, is not identical to the desired output signal. The difference between the output signal and the desired output signal is defined as noise. The desired output signal is updated so as to shift the noise outside the limited frequency bandwidth of interest, while keeping the portion of the output signal, which is within the limited frequency bandwidth of interest, as close as possible to the input signal.
One specific group of class D power amplifiers is called 1-bit power amplifiers. 1-bit power amplifiers produce only two levels of output voltage, wherein one level is defined zero and the other level is the voltage level feeding the power amplifier.
Reference is now made to FIGS. 1D and 1E, which are examples of a typical output signal of a class D power amplifier utilizing a 4-level power quantizer, for two different constant input signals (referenced VIN). Each output voltage level is selected to be applied to the output, during a time period T, wherein at the end of that time period, a new output voltage level is selected. It is noted that the new output voltage level can be identical to the former one. Time period T defines the operating frequency F of the N-level power quantizer 34, wherein F=1/T. According to class D theory, the operating frequency F should be significantly higher than the maximal frequency in the frequency bandwidth of interest. FIG. 1D illustrates an output signal, which is respective of a relatively high input signal. FIG. 1E illustrates an output signal, which is respective of a relatively low input signal.
The theoretical efficiency of a class D (1-bit) power amplifier for a full-scale sine shaped signal is about 83%. The theoretical efficiency for a full-scale typical speech or audio signal is about 47%. The power loss in a class D power amplifier resides in portions of the output signal, which are external to the frequency bandwidth of interest. For example, a class D audio power amplifier usually has a frequency bandwidth of interest of 20 Hz-20 KHz. The respective class D output signal includes a portion located between 20 Hz and 20 KHz which consumes about 47% of the total consumed power. The other portion of the-output signal is located above 20 KHz, regarded as noise and consumes all the rest of the power (i.e., about 53%).
It is customary to regard class A and class AB power amplifiers as time domain power amplifiers and class D power amplifiers as frequency domain power amplifiers. A class A or class AB power amplifier produces an output signal which is substantially identical in shape (up to DC bias at class A power amplifiers) to the input signal. A class D power amplifier produces an output signal, which is constructed of a discrete set of voltage levels (i.e., even two voltage levels are enough). These discrete voltage levels are applied to the load element, for constant periods of time. Hence, the shape of the output signal is not identical to that of the input signal. A class D power amplifier substantially duplicates the frequency bandwidth of interest of the input signal to the output signal, while shaping the noise outside these frequencies.
The above-disclosed architectures suffer from low power amplification efficiency. Other architectures, which are known in the art, attempt to overcome this disadvantage.
One type of such architectures utilizes a plurality of power sources and a time domain power amplifier, also referred to as class G power amplifiers. Reference is now made to FIG. 1F, which is a schematic illustration of a power amplifier having multiple power sources, generally referenced 40, which is known in the art. Amplifier 40 includes a controller 42, a power source monitor 44, a power source array 46 and a time domain power amplifier 48. Controller 42 is connected to power source monitor 44 and to power source array 46. Power source array 46 is further connected to time domain power amplifier 48 and to power source monitor 44.
Controller 42 and time domain power amplifier 48 receive an input signal X(t). Power source monitor 44 measures the voltage levels of all the power sources of power source array 46 and provides the respective readings to controller 42. Controller 42 approximates a desired output signal according to the input signal and selects a power source from power source array 46, according to the desired output signal. The selected power source exhibits the lowest voltage level (out of the voltage levels available in power source array 46), which is higher than the desired output signal. Controller 42 connects the selected power source to time domain power amplifier 48, which in turn produces the desired output signal according to the input signal X(t). It is noted that loss of power in time domain amplifier architectures such as class A and class AB, mainly resides in the difference between the supplied power source voltage and the output voltage applied to the load. This architecture reduces this difference by selecting a power source having a voltage, which is closest to the output voltage applied to the load, thereby reducing power loss.
Examples of this kind of architecture are shown in U.S. Pat. No. 4,598,255 to Hong, entitled xe2x80x9cPower Amplifier Apparatusxe2x80x9d, in U.S. Pat. No. 3,961,280 to Sampei, entitled xe2x80x9cAmplifier Circuit Having Power Supply Voltage Responsive to Amplitude of Input Signalxe2x80x9d and in U.S. Pat. No. 3,772,606 to Waehner, entitled xe2x80x9cMulti-Level Power Amplifierxe2x80x9d.
Another type of such architectures utilizes a single power source coupled with a voltage tracker and a time domain power amplifier, also referred to as class H power amplifiers. Reference is now made to FIG. 1G, which is a schematic illustration of a voltage tracking power amplifier, generally referenced 50, which is known in the art. Amplifier 50 includes a power source 52, a voltage tracker 54 and a time domain power amplifier 56. Voltage tracker 54 is connected to power source 52 and to time domain power amplifier 56.
Voltage tracker 54 and time domain power amplifier 56 receive an input signal X(t). Voltage tracker 54 approximates the desired output signal according to the input signal. Voltage tracker 54 efficiently reduces the voltage level, provided by power source 52, to a level, which is a little higher than the voltage of the desired output signal, thereby reducing power loss. Voltage tracker 54 provides the reduced voltage level to time domain power amplifier 56, which in turn produces the desired output signal according to the input signal X(t). It is noted that the reduction in power loss mainly depends on the efficiency of voltage tracker 54 and its ability to track the desired output signal.
Examples for this kind of architecture are shown in U.S. Pat. No. 4,218,660 to Carver, entitled xe2x80x9cAudio Amplifier and Method for Apparatusxe2x80x9d, in U.S. Pat. No. 5,396,194 to Williamson et al., entitled xe2x80x9cAudio Frequency Power Amplifiersxe2x80x9d and in U.S. Pat. No. 5,101,172 to Ikeda et al., entitled xe2x80x9cLinear Amplifierxe2x80x9d.
A further type of such architectures utilizes a frequency domain power amplifier, which is coupled at the output thereof to a passive reactive low-pass filter, also referred to as improved class D power amplifiers. Reference is now made to FIG. 1H, which is a schematic illustration of a filtered frequency domain power amplifier, generally referenced 60, which is known in the art. Amplifier 60 includes a frequency domain power amplifier 62, a passive reactive low-pass filter 64 and a power source 66. Frequency domain power amplifier 62 is connected to passive reactive low-pass filter 64 and to power source 66. Frequency domain power amplifier 62 produces a class D type output signal, which includes a portion residing within the frequency bandwidth of interest and another portion, defined as noise, residing outside the frequency bandwidth of interest. Passive reactive low-pass filter 64 is tuned so as to allow only the portion of the class D type output signal, which resides in the frequency bandwidth of interest, to pass there through. Passive reactive low-pass filter 64 returns the energy of the noise portion of the output signal, back to frequency domain power amplifier 62. Theoretically, passive reactive low-pass filter 64 serves as a power reservoir, which collects most of the power of the noise and thus serves as a secondary power source to the frequency domain power amplifier 62. This architecture reduces power loss by storing the energy of the noise in the reactive elements of passive reactive low-pass filter 64 and returning this energy back to the system. An Example of this kind of architecture is shown in U.S. Pat. No. 4,178,556 to Attwood, entitled xe2x80x9cClass D Amplifier Systemxe2x80x9d.
Systems for controlling power supply output signals, using capacitors as temporary power sources, are known in the art. Conventional switched power supplies, DC to DC converters and AC to DC converters, which are known in the art, use capacitors as controlled temporary power sources, by connecting the capacitors either in series, parallel or mixed architecture, to the load. Examples for such devices are shown in U.S. Pat. No. 5,960,898 to Okada et al., entitled xe2x80x9cPower Supply Unit and Electric Vehicle Incorporating the Samexe2x80x9d and in JP Patent application No. 11-052411 to Okamura et al., entitled xe2x80x9cSwitching Connection Control Capacitor Power Supplyxe2x80x9d.
Other applications, use capacitor switching for reducing the effective resistance of a constant power source, by switching a capacitor in parallel to the power source, when required. An example of such architecture is shown in U.S. Pat. No. 6,097,973 to Rabe et al, entitled xe2x80x9cElectronic Circuit for a Portable Electronic Devicexe2x80x9d.
It is an object of the disclosed technique to provide a novel method and system for amplifying an input signal which overcome the disadvantages of the prior art.
In accordance with the disclosed technique, there is thus provided an amplifier, receiving an input signal to be amplified and provided to a respective load element. The amplifier includes a switch, a shaper, a power source array, a power reservoir array and a controller. The switch is connected to the load element. The power source array and the power reservoir array are connected to the switch. The controller is connected to the shaper and to the switch. The power source array includes at least one power source and the power reservoir array includes at least one power reservoir.
The switch produces a respective switch output signal for each the input signals. The shaper determines a respective shaper output signal, for each of the input signals, according to the input signal and a respective switch output signal. The controller determines a switching scheme according to the shaper output signals. The switch applies the switching scheme to the load element, to the power source array and to the power reservoir array.
In accordance with another aspect of the disclosed technique, there is thus provided an amplifier, receiving an input signal to be amplified and provided to a load element. The amplifier includes an active load, a switch connected to the active load, a shaper, a power source array, a power reservoir array, and a controller. The power source array is connected to the switch. The power source array includes at least one power source. The power reservoir array is connected to the switch. The controller is connected to the shaper and to the switch.
The active load provides an active load output signal to the load element. The shaper determines a shaper output signal, according to the input signal and the active load output signal. The controller determines a switching scheme, according to the shaper output signal. The switch applies the switching scheme to the power source array, to the power reservoir array and further to the active load. The active impedance of the active load is determined according to the system signals provided by the system.
In accordance with a further aspect of the disclosed technique, there is thus provided an amplifier, receiving an input signal to be amplified and provided to a respective load element. The amplifier includes a switch, a shaper, a power source array, a power reservoir array, an active load array and a controller. The switch is connected to the load element. The power source array and the power reservoir array are connected to the switch. The active load array is connected to the switch. The controller is connected to the shaper and to the switch.
The switch produces a respective switch output signal for each the input signals. The shaper determines a respective shaper output signal, for each the input signals, according to the input signal and a respective switch output signal. The active load array includes at least one active load element. The controller determines a switching scheme according to the shaper output signal. The switch applies the switching scheme to the load element, to the power source array and to the power reservoir array. The active impedance of selected ones of the active elements is determined according to system signals provided by the system.
In accordance with another aspect of the disclosed technique, there is thus provided a method for amplifying an input signal and providing the amplified input signal to a respective load element. The method includes the steps of analyzing each of the input signals and the respective feedback signal, determining a switching scheme for a subsequent best output signal, and applying the switching scheme to the load element.
The subsequent best output signal is determined by analyzing each of the input signals and the respective feedback signal. The respective subsequent best output signal is applied to the respective load element.